1. Field of the Invention
The present invention relates to an information processing apparatus having a cache, and to a cache-tag control method in an information processing apparatus.
2. Description of Related Art
In recent years, there has been an increasing demand for improvement in the reliability of computer systems. Further, along with this demand, there has also been a demand for improvement in the reliability of cache tags. A conventional method of controlling cache tags has employed a checking mechanism such as a parity check or the like. However, there has been no mechanism for correcting error tags.
Accordingly, there has been a dilemma in that while it is desired to provide cache tags with an error detecting and correcting function like ECC (error checking and correction), the execution of the ECC function in the cache tags fails to decrease a cycle time though a high-speed operation is required. This results in deterioration in system performance. Further, the addition of the ECC function to tag data having a smaller data width than that of the cache data leads to an increase in hardware volume of additional circuits such as a syndrome code generator circuit and error detecting and correcting circuits. Although this addition increases the system reliability, this has a problem of cost increase. Further, in order to improve the reliability of memories, there has been a conventional method of duplexing data and holding one data in an inverted format as a measure for compensating for an error in other one bit data. However, there has been no means for applying this method to the tag data.
In an information processing apparatus having a cache, with an error checking function held in a cache tag, it is an object of the present invention to provide a cache-tag control method capable of correcting an error in tag data by using a duplexed shadow-tag based on an error detecting method with a smaller volume of circuits, and capable of keeping the high-speed operation of the system at the same time.
Further, it is another object of the invention to provide an information processing apparatus for realizing the above-described cache-tag control method.
The present invention has been made to achieve the above objects.
The present invention is applied to an information processing apparatus having a cache, and having an error checking function in a cache tag. A true-tag which is data of a cache tag with an error check bit and a shadow-tag which is data having an inverted polarity of the true-tag are stored in separate addresses within one and the same tag-RAM. At the time of retrieving tags, the true-tag and the shadow-tag are retrieved one by one to carry out an error check. When there is no error in the true-tag, a hit decision is made by using this true-tag. When there is an error in the true-tag and there is no error in the shadow-tag, a hit decision is carried out by using the shadow-tag.
In the present invention, it is also possible to store the true-tag and the shadow-tag in identical addresses within separate tag-RAMs. In this case, at the time of retrieving tags, the true-tag and the shadow-tag are retrieved at the same time to carry out an error check. As a result of the error checking, a hit decision is made by using a tag in which there is no error.
According to both methods described above, in an information processing apparatus having a cache, with an error checking function held in a cache tag, it is possible to obtain a cache-tag control method capable of correcting an error in tag data by using a duplexed shadow-tag based on an error detecting method with a smaller volume of circuits, and capable of keeping high-speed operation of the system at the same time.